It is well known that memory devices store data which is used by other systems to execute certain functions. Such data can be as simple as multimedia files or user readable documents, and the memory devices that store such data can be non-volatile memory such as portable USB drives, various known memory cards and solid state hard disk drives, by example. Such memory devices can be volatile memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM) by example. In these cases, the memory devices can be standalone semiconductor memory chips encapsulated in a package.
Another type of data is more sensitive, such as encryption keys or passwords that are stored in a memory device and read out by a host system when needed. Such data can be stored in a memory device integrated with other circuits, such as in an application specific integrated circuit (ASIC) or other mixed circuit system. Alternately, a standalone memory device can be interconnected with a host system on a printed circuit board or in a multi-chip package to provide the storage capability.
Naturally, such sensitive data should be secure from intentional and unintentional discovery. While reverse engineering of semiconductor memory devices might be possible to discover the stored data, the cost to do so is very high as it requires specialized equipment to reveal physical circuit elements. Furthermore, companies who specialize in reverse engineering of semiconductor devices are unlikely to engage in the illicit act of unauthorized access of such sensitive data.
There has arisen a form of reverse engineering that can be used to partially determine the stored data in the memory device. This technique is referred to as power signature analysis, in which the power supply of the semiconductor memory device or the system the memory device is a part of, is monitored as the system is operated to execute various functions. The principle here is that particular data read out may exhibit a power consumption level that changes when different data states are read out, eventhough the actual data being read out is not known. So, as different read operations are executed by the memory device, power consumption will occur and the power supply will exhibit variations in its level. Patterns of the power supply variations can be correlated with particular functions over time (a clock signal), and when sufficient data is accumulated, analysis of the patterns may provide a clue as to the logic states of the data that is being accessed.
To illustrate the power signature problem with current memory devices, reference is made to FIG. 1. FIG. 1 is a schematic showing a known memory array and output path circuitry. The memory array is represented by bitlines BL0 to BL7 and a wordline WL, and it is assumed there is one memory cell connected at the intersection of the wordline WL with each bitline. Those skilled in the art understand that a memory array can include more than one wordline and the eight bitlines shown in FIG. 1. The memory array can consist of non-volatile or volatile memory cells. Bitlines BL0-BL3 are connected to a first column selection circuit 10 represented by a multiplexor/demultiplexor symbol, while bitlines BL4-BL7 are connected to a second column selection circuit 12 represented by multiplexor/demultiplexor symbol. Column selection circuits 10 and 12 are controlled by column selection signals (not shown) to couple one bitline to a databus line DB0 and DB1.
To read data, sense amplifiers 14 and 16 each compares voltages on DB0 and DB1 respectively against a reference voltage VREF for output on ports Q0 and Q1. The VREF voltage is set to a voltage level to distinguish a bitline voltage as being representative of a logic “1” or a logic “0”. This is more commonly known as single ended sensing. Output port Q0 outputs one bit of data, while output port Q1 outputs a second bit of data. To write data, write drivers 18 and 20 receive write data from input ports D0 and D1 for application to DB0 and DB1. The column selection circuits 10 and 12 are again controlled by selection signals to couple DB0 and DB1 to selected bitlines, where WL is driven to access the memory cells to effect storage of the data to the memory cells connected to the selected bitlines. Elements 10, 12, 14 and 16 can be considered the output path circuitry of FIG. 1.
An example read operation timing diagram for the circuit of FIG. 1 is shown in FIG. 2, where successive bits are read out from output ports Q0 and Q1 at each clock cycle CLK. In this example, power consumption occurs in the memory array and in the sense amplifiers 14 and 16 each time Q0 (or Q1) transitions from a low logic state to a high logic state. Furthermore, different power consumption can occur during high to low level transitions versus low to high level transitions. As shown in FIG. 2, there may be one level of power consumption when just a single output port transitions to the high logic state, a different level of power consumption when neither output port transitions to the high logic state, and yet another different level of power consumption when both output ports transition to the high logic state. While the instantaneous power consumption at a particular clock cycle can be monitored, the sequence of transitions of the output ports over successive clock cycles can also be used to determine a power signature of the memory device.
It is, therefore, desirable to provide a memory device configured to suppress any power signature during read operations.